# Desired Features for a PLONK Optimising Compiler

**URL:** <https://www.plonk.cafe/t/desired-features-for-a-plonk-optimising-compiler/69>\
**Category:** Uncategorized\
**Created:** [17 June 2020 17:19 UTC](https://www.plonk.cafe/t/desired-features-for-a-plonk-optimising-compiler/69 "2020-06-17T17:19:04Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![jon-chuang](https://dub1.discourse-cdn.com/flex017/user_avatar/www.plonk.cafe/jon-chuang/32/35_2.png) [@jon-chuang](https://www.plonk.cafe/u/jon-chuang)\
**Post date:** [17 June 2020 17:19 UTC](https://www.plonk.cafe/t/desired-features-for-a-plonk-optimising-compiler/69/1 "2020-06-17T17:19:04Z")

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Compiler front end:

- Standard things: Constant subexpression elimination etc.

Backend (gates and constraints):

- Automatic custom gate synthesis for repeated basic blocks
- Cost model for balancing proof size, prover exponentiations, maximum gate arity, gate depth.
- Partitioning the circuit to combine multiple constraints into single domain eval (“row”).
  - Furthermore, partitions need not be disjoint. With large arity or otherwise, one is likely to be able to eval multiple constraints per domain on overlapping subsets in a single “row” or “window”. Examples: single-constraint matrix multiplication, single-constraint batch inversion.

- For tables, choosing the right table sizes.

Thoughts:

- Just like real compilers, best solutions will involve approximate optimisation with empirical benchmarks

Literature:

- Compiler
- VLSI